IBIS Macromodel Task Group

Meeting date: 24 February 2015

Members (asterisk for those attending):
Altera:                       David Banas
ANSYS:                      * Dan Dvorscak
                            * Curtis Clark
Avago (LSI)                   Xingdong Dai
Cadence Design Systems:     * Ambrish Varma
                              Brad Brim
                              Kumar Keshavan
                              Ken Willis
Ericsson:                     Anders Ekholm
IBM                           Steve Parker
Intel:                      * Michael Mirmak
Keysight Technologies:      * Fangyi Rao
                            * Radek Biernacki
Maxim Integrated Products:    Hassan Rafat
Mentor Graphics:            * John Angulo
                            * Arpad Muranyi
Micron Technology:          * Randy Wolff
                              Justin Butterfield
QLogic Corp.                  James Zhou
                              Andy Joy
eASIC                         Marc Kowalski
SiSoft:                     * Walter Katz
                              Todd Westerhoff
                            * Mike LaBonte
Synopsys                      Rita Horner
Teraspeed Consulting Group:   Scott McMorrow
Teraspeed Labs:             * Bob Ross

(Note: Agilent has changed to Keysight)

The meeting was led by Arpad Muranyi.

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Opens:

- Mike L: Bob and I have a question about AMI reserved words.


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Call for patent disclosure:

- None


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Review of ARs:

- Michael M update IBIS-AMI Direction proposal.
  - An update to remove "confidential" was done last week.
  - A technical update is in progress.
  - Feedback has been received.
  - May be able to present next week.

- Arpad to review IBIS specification for min max issues.
  - In progress.
  - This has come up in the new interconnect proposal and should be addressed there.


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New Discussion:

Backchannel and Optimization:
- Walter reported no progress, he has been on vacation.

Buffer Impedance and C_comp Improvements:
- Randy: Nothing is prepared for presentation this week.

Repeaters:
- Fangyi and Walter reported no progress.

AMI Reserved Words:
- Mike L showed an AMI file.
- Mike L: Each Model_Specific parameter is named with an AMI reserved word.
  - IBISCHK6 finds nothing wrong at all.
  - This calls into question the meaning of "reserved word".
- Radek: There is no problem here, it is reserved only in the context of
  being under a parameter, not at parameter level.

Bob Ross C_comp discussion from DesignCon summit:

- Bob showed his C_comp presentation from the DesignCon summit.
- Slide 2:
  - Bob: The K-tables enable and disable the I-V curves gradually as the buffer transitions.
  - Walter: In steady state on K=1 and when off K=0.
    - The fundamental fallacy is that you can represent a buffer by turning those on and off.
  - Bob: It's not how buffers work, it's just a model that works fairly well.
- Slide 5:
  - Bob: A more complex C_comp still has constant values.
    - They might be placed in different corners.
- Slide 9:
  - Bob: A multiplier is used to create the K functions from the output waveform and a reference.
    - This has a feedback loop.
    - It uses 2 different loads to solve the 2 unknowns.
- Slide 10:
  - Bob: The feedback loop accounts for the reactive fixture elements.
- Slide 12:
  - Bob: SPICE extrapolation can cause some issues.
  - Arpad: Does it matter what kind of interpolation is best?
    - Are sharp corners OK or should they be rounded?
  - Bob: Sharp corners are OK.
- Slide 16:
  - Bob: This is a revised scheme.
    - The feedback loop includes clamps and all other elements.
    - The voltage and current to converge can be sensed.
- Slide 18:
  - Bob: This can be used to eliminate reactive elements from the IBIS model.
- Slide 20:
  - Bob: We can devise an ideal test circuit.
- Slide 21:
  - Bob: This shows the extracted K curves for different C loads.
- Slide 22:
  - Bob: This shows the extracted K curves with reactive LC loads.
- Slide 24:
  - Bob: The number of points used is not a major factor.
    - On-die packages created problems, the results were not as accurate.
    - Sharp interpolation corners might have interacted here.

- Arpad: On slide 21 are those actual K tables?
  - It looks like it is over-clocking.
  - The K tables are long.
- Bob: The K tables were extracted over 2ns.
  - Pathological cases like 1F can throw this off.
- Walter: This breaks down with poor quality V-T curves.
  - There should be an option to put K tables into an IBIS file.
  - It would be a useful verification.
  - With more complex C_comp it would help EDA tools.
- Bob: We might want to specify V-T at the inner C_comp node.
- Walter: That might not be realistic.
- Arpad: Where should the V-T measurement point be?
  - Should IBIS have an option to do it either way?
- Walter: I sent an email about that.
  - V-T should be measured at the right side.
  - It should not include an on-die supplied independently.
- Arpad: On-die would be included in the C_comp model.
- Bob: On-die can be outside the model, according to the interconnect spec.
  - You should be able to measure at the pin and recreate at the pad or anywhere.
- Radek: There might be coupling, measurement conditionals need to be specified.
- Bob: I would not be confident in C_comp with coupling.
- Radek: Correspondence between tables requires that we be free from coupling.
- Walter: The IC vendor will decide where the point will be.

- Arpad: We should decide how to proceed.
  - There were proposals but not a BIRD.
- Walter: I had proposed "Final Stage Subckt".
  - Randy and I could work on this.

AR: Walter and Randy produce C_comp BIRD.

- Bob: The method I show is informational, not actually part of any C_comp BIRD.


Next week:

- Walter: We can discuss PAM4.
- Michael M: Next week I'll have something on interconnect.
- Arpad: Should TS 2.1 be discussed here or Wednesday?
- Michael M: Wednesday, but it should not interrupt interconnect BIRD work.
- Walter: Is binary in the draft?
- Michael M: The draft has it, 2.0 does not.
  - No work has been done since 2010.
- Walter: Sij is important.

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Next meeting: 02 Mar 2015 12:00pm PT
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IBIS Interconnect SPICE Wish List:

1) Simulator directives
